The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2012
Filed:
Aug. 05, 2010
James Leroy Deming, Madison, AL (US);
Mark Allen Mosley, Guntersville, AL (US);
William Craig Mcknight, Harvest, AL (US);
Emmett M. Kilgrariff, San Jose, CA (US);
Steven E. Molnar, Chapel Hill, NC (US);
Colyn Scott Case, Hyde Park, VT (US);
James Leroy Deming, Madison, AL (US);
Mark Allen Mosley, Guntersville, AL (US);
William Craig McKnight, Harvest, AL (US);
Emmett M. Kilgrariff, San Jose, CA (US);
Steven E. Molnar, Chapel Hill, NC (US);
Colyn Scott Case, Hyde Park, VT (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills.