The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Nov. 25, 2009
Applicants:

Naoki Takada, Yokohama, JP;

Naruhiko Kasai, Yokohama, JP;

Takuya Eriguchi, Yokosuka, JP;

Yuki Okada, Tama, JP;

Mitsuru Goto, Chiba, JP;

Yoshihiro Kotani, Chiba, JP;

Inventors:

Naoki Takada, Yokohama, JP;

Naruhiko Kasai, Yokohama, JP;

Takuya Eriguchi, Yokosuka, JP;

Yuki Okada, Tama, JP;

Mitsuru Goto, Chiba, JP;

Yoshihiro Kotani, Chiba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/038 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.


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