The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Jan. 19, 2007
Applicants:

Masaki Murase, Kanagawa, JP;

Daisuke Ito, Tokyo, JP;

Masaaki Tonogai, Tokyo, JP;

Yoshitoshi Kida, Kanagawa, JP;

Yoshiharu Nakajima, Kanagawa, JP;

Inventors:

Masaki Murase, Kanagawa, JP;

Daisuke Ito, Tokyo, JP;

Masaaki Tonogai, Tokyo, JP;

Yoshitoshi Kida, Kanagawa, JP;

Yoshiharu Nakajima, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A display device able to amplify the same input as a power supply voltage of IC by using low temperature polysilicon having high threshold voltage and large variation and an electronic apparatus using the same, including MCK use level shifters-and-of a type where a reset operation is periodically necessary, a logic circuitfor using a level shift horizontal synchronization signal Hsync to input reset pulses for the MCK level shifters-and-having a period ofhorizontal periods shifted in phase byhorizontal periods (note, M<N) to the level shifters-and-and outputting the resultant signals, and a function of selecting the circuit not performing the reset operation among outputs of thenumber of level shifters-and-for each M horizontal periods and outputting a level shift master clock LSMCK as a last output signal.


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