The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Jun. 27, 2012
Applicants:

Peter J. Mole, St. Albans, GB;

Philip V. Golden, Menlo Park, CA (US);

Inventors:

Peter J. Mole, St. Albans, GB;

Philip V. Golden, Menlo Park, CA (US);

Assignee:

Intersil Americas Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.


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