The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Nov. 04, 2008
Applicants:

Youichiro Nakahara, Tsu, JP;

Naoto Ikegawa, Hirakata, JP;

Kyohei Uemura, Tsu, JP;

Yoshiyuki Uchinono, Hirakata, JP;

Inventors:

Youichiro Nakahara, Tsu, JP;

Naoto Ikegawa, Hirakata, JP;

Kyohei Uemura, Tsu, JP;

Yoshiyuki Uchinono, Hirakata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/09 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit board includes: an insulating substrate; and a circuit formed on the insulating substrate. The circuit includes: a undercoat layer with a circuit pattern formed by irradiating a metal thin film covering a surface of the insulating substrate with a laser along an outer shape of the circuit so as to partly remove the metal thin film along the outer shape of the circuit; a Cu plating layer, a Ni plating layer and a Au plating layer formed by metal plating and sequentially provided on a surface of the undercoat layer. A first middle plating layer and a second middle plating layer are provided between the Ni plating layer and the Au plating layer. The first middle plating layer includes metal with a less noble standard electrode potential with respect to Au and is in contact with the Au plating layer. The second middle plating layer includes metal with a noble standard electrode potential with respect to the metal in the first middle plating layer and is in contact with the first middle plating layer.


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