The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2012

Filed:

Jan. 19, 2011
Applicants:

Suresh Kadiyala, Cupertino, CA (US);

Pius NG, Hillsboro, OR (US);

Anand Pandurangam, Sunnyvale, CA (US);

Satish Padmanabhan, Sunnyvale, CA (US);

James Player, Sunnyvale, CA (US);

Inventors:

Suresh Kadiyala, Cupertino, CA (US);

Pius Ng, Hillsboro, OR (US);

Anand Pandurangam, Sunnyvale, CA (US);

Satish Padmanabhan, Sunnyvale, CA (US);

James Player, Sunnyvale, CA (US);

Assignee:

Algotochip Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.


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