The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2012
Filed:
May. 07, 2010
Jason R. Baumgartner, Austin, TX (US);
Michael L. Case, Pflugerville, TX (US);
Robert L. Kanzelman, Rochester, MN (US);
Hari Mony, Austin, TX (US);
Jason R. Baumgartner, Austin, TX (US);
Michael L. Case, Pflugerville, TX (US);
Robert L. Kanzelman, Rochester, MN (US);
Hari Mony, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Mechanisms are provided in a design environment for eliminating, coalescing, or bypassing ports. The design environment comprises one mechanism to eliminate unnecessary ports in arrays using disabled and disconnected pin information. The design environment may comprise another mechanism to combine and reduce the number of array ports using address comparisons. The design environment may comprise another mechanism to combine and reduce the number of array ports using disjoint enable comparisons. The design environment may comprise one mechanism to combine and reduce the number of array ports using 'don't care' computations. The design environment may comprise another mechanism to reduce the number of array ports through bypassing write-to-read paths around arrays.