The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2012
Filed:
Apr. 09, 2009
Randall P. Fry, Greenville, NC (US);
Michael A. Minter, Bowling Green, KY (US);
Randall P. Fry, Greenville, NC (US);
Michael A. MInter, Bowling Green, KY (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.