Processing module, error correction decoding circuit, and processing method for error locator polynomial

Abstract

A Euclid processing module for obtaining an error locator polynomial of a binary BCH code in an error correction decoding circuit, in which error corrections of words are performed, includes registers, a shifter, a zero insertion unit, selectors and a sequencer. Coefficients of polynomials R(z) and B(z) stored in the registers are subjected to Galois field calculations by the processing module. Results of the calculations and the data of the registers are shifted by the shifter. Some of the coefficients are erased by the zero insertion unit and stored in registers by controlling the selectors with the sequencer. A necessary polynomial σ (z) is calculated by repeated processing of the processing module. The Euclid processing module decreases a logic scale and simplifies controlling logic in a state of small latency and high operating frequency.