The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2012
Filed:
Nov. 25, 2009
Xiaoyan Su, San Jose, CA (US);
Sriram Narayan, Pleasanton, CA (US);
Wilson Wong, San Francisco, CA (US);
Sergey Shumarayev, Los Altos Hills, CA (US);
Xiaoyan Su, San Jose, CA (US);
Sriram Narayan, Pleasanton, CA (US);
Wilson Wong, San Francisco, CA (US);
Sergey Shumarayev, Los Altos Hills, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Equalizer circuitry on an integrated circuit ('IC') includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.