Nonvolatile semiconductor memory device and discharge circuit thereof

Abstract

A discharge circuit for a floating gate type MOS memory cell transistor disposed in a memory array region of a nonvolatile semiconductor memory device, the memory cell region being formed in P-well, the P-well being formed in an N-well, and the N-well being formed in a P-type semiconductor substrate, includes a word line discharge circuit providing a word line control voltage and a bulk discharge circuit providing a voltage to the P-well during a discharge operation. Constant current transistors and switching transistors in the word line discharge circuit and the bulk discharge circuit are simultaneously turned ON during at least a portion of the discharge operation.