The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Apr. 19, 2011
Applicants:

Jae-sup Lee, Suwon-si, KR;

Kang-yoon Lee, Seoul, KR;

An-soo Park, Seoul, KR;

Young-gun Pu, Seoul, KR;

Joon-sung Park, Seoul, KR;

Inventors:

Jae-Sup Lee, Suwon-si, KR;

Kang-Yoon Lee, Seoul, KR;

An-Soo Park, Seoul, KR;

Young-Gun Pu, Seoul, KR;

Joon-Sung Park, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A Time-to-Digital Converter (TDC) is provided. The TDC includes a first TDC unit for receiving a first input signal and a second input signal, delaying the first input signal on a specific time basis using each of first delay blocks, generating first phase-divided signals by performing first phase division on signals of input/output nodes for each of the first delay blocks on a predefined Phase-Interpolation (PI) delay time basis, and outputting the second input signal and a phase-divided signal closest to the second input signal, among the first phase-divided signals, a time amplifier for independently time-amplifying the second input signal and the phase-divided signal closest to the second input signal, and a second TDC unit for delaying a phase-divided signal closest to the time-amplified second input signal on a specific time basis using each of second delay blocks, and generating second phase-divided signals by performing second phase division on signals of input/output nodes for each of the second delay blocks on a predefined PI delay time basis.


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