The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2012
Filed:
Mar. 11, 2011
Ludmil Nikolov, Chippenham, GB;
Carlos Calisto, Swindon, GB;
Ludmil Nikolov, Chippenham, GB;
Carlos Calisto, Swindon, GB;
Dialog Semiconductor GmbH, Kirchheim/Teck-Nabern, DE;
Abstract
Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation. A Dynamic Control of the Commutating Components ensures least disturbance of the voltage potentials, thus allowing shorter ON times and respectively better power efficiency. The invention can also be applied to reference voltage and to bias current generator circuits.