The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Mar. 13, 2012
Applicants:

Kaoru Katoh, Mitaka, JP;

Shigeki Koya, Koganei, JP;

Shinichiro Takatani, Mitaka, JP;

Yasushi Shigeno, Maebashi, JP;

Akishige Nakajima, Higashiyamato, JP;

Takashi Ogawa, Tokyo, JP;

Inventors:

Kaoru Katoh, Mitaka, JP;

Shigeki Koya, Koganei, JP;

Shinichiro Takatani, Mitaka, JP;

Yasushi Shigeno, Maebashi, JP;

Akishige Nakajima, Higashiyamato, JP;

Takashi Ogawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 6/687 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit which reduces and increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.


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