Variable unit delay circuit and clock generation circuit for semiconductor apparatus using the same

Abstract

A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.