The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Nov. 08, 2010
Applicants:

Jung-ho Lee, Goyang, KR;

Eun-chul Kang, Seoul, KR;

Won-hi OH, Bucheon, KR;

Inventors:

Jung-ho Lee, Goyang, KR;

Eun-Chul Kang, Seoul, KR;

Won-Hi Oh, Bucheon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals.


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Lee, Jung-ho. (2012). Interlock circuit and interlock system including the same (U.S. Patent No. 8330490). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8330490

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