The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2012
Filed:
May. 26, 2009
Romano Hoofman, Geel, BE;
Remco Henricus Wilhelmus Pijnenburg, Hoogeloon, NL;
Youri Victorovitch Ponomarev, Leuven, BE;
Romano Hoofman, Geel, BE;
Remco Henricus Wilhelmus Pijnenburg, Hoogeloon, NL;
Youri Victorovitch Ponomarev, Leuven, BE;
NXP B.V., Eindhoven, NL;
Abstract
The invention relates to a integrated circuit comprising an electronic circuit integrated on a substrate (), and further comprising protections means for protection of the electronic circuit (). The protection means comprise: i) a first strained encapsulation layer () being provided on a first side of the substrate (), wherein the first strained encapsulation layer () has a strain (S) in a direction parallel to the substrate (), and ii) disabling means () arranged for at least partially disabling the electronic circuit () under control of a strain change in the substrate (). The invention further relates to a method of manufacturing such integrated circuit, and to a system comprising such integrated circuit. Such system is selected from a group comprising: a bank-card, a smart-card, a contact-less card and an RFID. All embodiments of the integrated circuit in accordance with the invention provide essentially an alternative tamper protection to the data stored or present in the electronic circuit therein. A first main group of embodiments concerns an integrated circuit wherein tamper protection is obtained by detecting a strain change during tampering and subsequently disabling the electronic circuit. A second main group of embodiments concerns an integrated circuit wherein tamper protection is obtained by designing a stack of strained encapsulation layers, such that tampering causes releasing of strain and thereby mechanical disintegrate (break, delaminate, etc) of the integrated circuit, and thus disabling the electronic circuit.