The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Nov. 01, 2007
Applicants:

Jeffrey Lee Large, Dallas, TX (US);

Henry Litzmann Edwards, Garland, TX (US);

Ayman A. Fayed, Wylie, TX (US);

Patrick Cruise, Dallas, TX (US);

Kah Mun Low, Richardson, TX (US);

Neeraj Nayak, Richardson, TX (US);

Oguz Altun, Plano, TX (US);

Chris Barr, Plano, TX (US);

Inventors:

Jeffrey Lee Large, Dallas, TX (US);

Henry Litzmann Edwards, Garland, TX (US);

Ayman A. Fayed, Wylie, TX (US);

Patrick Cruise, Dallas, TX (US);

Kah Mun Low, Richardson, TX (US);

Neeraj Nayak, Richardson, TX (US);

Oguz Altun, Plano, TX (US);

Chris Barr, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.


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