The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Dec. 23, 2009
Applicants:

Hee-dong Choi, Seosan-si, KR;

Ki-sul Cho, Gumi-si, KR;

Hye-young Choi, Seoul, KR;

Doo-seok Yang, Incheon, KR;

Byeong-gyu Roh, Seoul, KR;

Inventors:

Hee-Dong Choi, Seosan-si, KR;

Ki-Sul Cho, Gumi-si, KR;

Hye-Young Choi, Seoul, KR;

Doo-Seok Yang, Incheon, KR;

Byeong-Gyu Roh, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first passivation layer; forming a second passivation layer on a surface of the first passivation layer including the gate line formed thereon; and forming a pixel electrode on the second passivation layer.


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