The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2012

Filed:

Apr. 05, 2011
Applicant:

Joseph Pernyeszi, Scotts Valley, CA (US);

Inventor:

Joseph Pernyeszi, Scotts Valley, CA (US);

Assignee:

General Microelectronics Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A planar, monolithic, high-voltage (HV), integrated circuit (IC) includes power field-effect-transistors (FETs) and/or bipolar power-transistors having an HV diffusion connection. The HV IC further includes several types of HV, low-current (LC) FETs including depletion and/or enhancement mode transistors and/or HV-LC bipolar transistors. The HV-LC transistors are integrated into the HV-high-current (HC) or power transistor structure in various combinations by sharing their HV diffusion connections, which enables increased design versatility while minimizing die area. Isolation and buried diffusion structures provide higher operating voltage and/or enhanced depletion FET shut-off. HV-LC IGFET body and/or bipolar transistor base regions are either isolated from or connected to the grounded isolation diffusion further enhancing design versatility.


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