The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2012

Filed:

Nov. 17, 2009
Applicant:

Christer Jansson, Linköping, SE;

Inventor:

Christer Jansson, Linköping, SE;

Assignee:

CSR Technology Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A latched comparator circuit comprises an input amplification unit, a buffer unit, and a control unit. The input amplification unit comprises a first and a second input terminal for receiving a first and a second input voltage, respectively, of the latched comparator circuit. The input amplification unit further comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the input amplification unit. In addition, the input amplification unit comprises a reset terminal arranged to receive a reset signal for resetting the input amplification unit. The buffer unit is operatively connected to the first and the second output terminal of the input amplification unit. Furthermore, the buffer unit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the buffer unit. The control unit is operatively connected to the input amplification unit and the buffer unit. The control unit is adapted to generate the reset signal based on the first and the second output voltage of the buffer unit and a clock signal and to generate an output signal of the latched comparator circuit based on the first and the second output voltage of the buffer unit. A method of operating the latched comparator circuit is also disclosed.


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