The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2012
Filed:
Sep. 05, 2006
Vance D. Archer, Iii, Greensboro, NC (US);
Michael C. Ayukawa, Ecublens, CH;
Mark A. Bachman, Sinking Springs, PA (US);
Daniel P. Chesire, Winter Garden, FL (US);
Seung H. Kang, Sinking Springs, PA (US);
Taeho Kook, Orlando, FL (US);
Sailesh M. Merchant, Macungie, PA (US);
Kurt G. Steiner, Foglesville, PA (US);
Vance D. Archer, III, Greensboro, NC (US);
Michael C. Ayukawa, Ecublens, CH;
Mark A. Bachman, Sinking Springs, PA (US);
Daniel P. Chesire, Winter Garden, FL (US);
Seung H. Kang, Sinking Springs, PA (US);
Taeho Kook, Orlando, FL (US);
Sailesh M. Merchant, Macungie, PA (US);
Kurt G. Steiner, Foglesville, PA (US);
Agere Systems LLC, Wilmington, DE (US);
Abstract
The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.