The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2012

Filed:

Feb. 04, 2010
Applicants:

Kelageri Nagaraj, San Diego, CA (US);

Satish K. Raj, San Diego, CA (US);

Venugopal Sanaka, San Diego, CA (US);

Raghavendra C. Dasegowda, San Diego, CA (US);

Inventors:

Kelageri Nagaraj, San Diego, CA (US);

Satish K. Raj, San Diego, CA (US);

Venugopal Sanaka, San Diego, CA (US);

Raghavendra C. Dasegowda, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.


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