The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8316264 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 20, 2012

Filed:

Sep. 09, 2010
Applicant:

Yoshikazu Iizuka, Kanagawa, JP;

Inventor:

Yoshikazu Iizuka, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one embodiment, electrical test results of a semiconductor memory arrayed in a logical address order are stored in a first memory secured in a main memory, a plurality of second memory areas in each of which loading and storing of each data in a unit size is performed is secured in the main memory, FBMs in which pass/fail information is arrayed in a physical address order are generated based on different parts of the electrical test results stored in the first memory area, respectively, the FBMs generated from the different parts of the electrical test results are stored in the second memory areas, respectively, and the FBMs stored in the second memory areas, respectively, are output.


Find Patent Forward Citations

Iizuka, Yoshikazu. (2012). Failure analysis method, failure analysis apparatus, and computer program product (U.S. Patent No. 8316264). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8316264

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