The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2012

Filed:

Dec. 30, 2009
Applicants:

Greg H. Bellows, Austin, TX (US);

Jason N. Dale, Austin, TX (US);

Brian H. Horton, Pflugerville, TX (US);

Joaquin Madruga, Round Rock, TX (US);

Inventors:

Greg H. Bellows, Austin, TX (US);

Jason N. Dale, Austin, TX (US);

Brian H. Horton, Pflugerville, TX (US);

Joaquin Madruga, Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.


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