The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2012

Filed:

Jul. 18, 2011
Applicants:

Seyed Jafar Jafarian-tehrani, Fremont, CA (US);

Ralph Jan-pin LU, Fremont, CA (US);

Inventors:

Seyed Jafar Jafarian-Tehrani, Fremont, CA (US);

Ralph Jan-Pin Lu, Fremont, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01T 23/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A plasma processing system for processing a wafer is provided. The system includes an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support the wafer. The ESC includes a positive terminal for providing a first force to the wafer and a negative terminal for providing a second force to the wafer. The system also includes a first circuit arrangement configured to measure at least a first voltage for determining a value of a positive load current applied to the positive terminal. The system further includes a second circuit arrangement configured to measure at least a second voltage for determining a value of a negative load current applied to the negative terminal. The system yet also includes circuitry configured to adjust a bias voltage using the values of the positive load current and the negative load current for balancing the first force and the second force.


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