The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2012

Filed:

May. 14, 2008
Applicant:

Shunzou Ohshima, Kosai, JP;

Inventor:

Shunzou Ohshima, Kosai, JP;

Assignee:

Yazaki Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/00 (2006.01); H02H 3/08 (2006.01); H02H 9/02 (2006.01); H02H 9/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

An overcurrent protection apparatus which, when a layer short or a dead short occurs in a load circuit, interrupts the circuit in accordance with respective situations, whereby the load circuit is protected is provided. The apparatus includes a first overcurrent detecting section for detecting a counter electromotive force generated in a power supply wiring, and a second overcurrent detecting section, disposed in each of the plural load circuits, for detecting that a load current ID becomes an overcurrent. The apparatus includes a delaying section for outputting a delay signal at a first delay time when an overcurrent is detected by the second overcurrent detecting section, and for outputting the delay signal at a second delay time which is shorter than the first delay time when an overcurrent is detected by both of the first overcurrent detecting section and the second overcurrent detecting section. According to the configuration, in the case of the occurrence of a layer short, the load circuit can be interrupted at the first delay time, and, in the case of the occurrence of a dead short, the load circuit can be interrupted at the second delay time.


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