The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2012
Filed:
Apr. 26, 2010
Michael D. Hutton, Mountain View, CA (US);
James G. Schleicher, Ii, Los Gatos, CA (US);
Daniel R. Mansur, Emerald Hills, CA (US);
Michael D. Hutton, Mountain View, CA (US);
James G. Schleicher, II, Los Gatos, CA (US);
Daniel R. Mansur, Emerald Hills, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A field programmable gate array ('FPGA') is provided having integrated application specific integrated circuit ('ASIC') fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.