The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2012
Filed:
Sep. 16, 2009
Chien-hung Chen, Taipei, TW;
Lih-hsiung Chan, Kaohsiung, TW;
Chin-yueh Liao, Taipei, TW;
Hsien-kai Tseng, Taoyuan County, TW;
Chien-Hung Chen, Taipei, TW;
Lih-Hsiung Chan, Kaohsiung, TW;
Chin-Yueh Liao, Taipei, TW;
Hsien-Kai Tseng, Taoyuan County, TW;
Au Optronics Corporation, Hsinchu, TW;
Abstract
A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.