The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8314001 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 20, 2012

Filed:

Apr. 09, 2010
Applicants:

Todd Alan Christensen, Rochester, MN (US);

Phil Christopher Felice Paone, Rochester, MN (US);

David Paul Paulsen, Dodge Center, MN (US);

John Edward Sheets, Ii, Zumbrota, MN (US);

Inventors:

Todd Alan Christensen, Rochester, MN (US);

Phil Christopher Felice Paone, Rochester, MN (US);

David Paul Paulsen, Dodge Center, MN (US);

John Edward Sheets, II, Zumbrota, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.


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Christensen, Todd. (2012). Vertical stacking of field effect transistor structures for logic gates (U.S. Patent No. 8314001). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8314001

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