The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2012
Filed:
Sep. 02, 2009
Method for generating layout pattern of semiconductor device and layout pattern generating apparatus
Tomoyuki Inoue, Kanagawa, JP;
Tomoyuki Inoue, Kanagawa, JP;
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Abstract
In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell.