The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2012

Filed:

Mar. 13, 2009
Applicants:

Stuart Z. Jacobs, Lakeville, MN (US);

David A. Larson, Rochester, MN (US);

Wade B. Ouren, Rochester, MN (US);

Edward C. Prosser, Rochester, MN (US);

Kenneth C. Vossen, Rochester, MN (US);

Inventors:

Stuart Z. Jacobs, Lakeville, MN (US);

David A. Larson, Rochester, MN (US);

Wade B. Ouren, Rochester, MN (US);

Edward C. Prosser, Rochester, MN (US);

Kenneth C. Vossen, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Dynamic control of memory affinity is provided for a shared memory logical partition within a shared memory partition data processing system having a plurality of nodes. The memory affinity control approach includes: determining one or more home node assignments for the shared memory logical partition, with each assigned home node being one node of the plurality of nodes of the system; determining a desired physical page level per node for the shared memory logical partition; and allowing the shared memory partition to run and using the home node assignment(s) and its desired physical page level(s) in the dispatching of tasks to physical processors in the nodes and in hypervisor page memory management to dynamically control memory affinity of the shared memory logical partition in the data processing system.


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