The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2012

Filed:

Feb. 20, 2008
Applicants:

Yung-cheng MA, Hsinchu, TW;

I-yen Chen, Kaohsiung, TW;

Yen-tun Peng, Taipei, TW;

Chi-lung Wang, Hsinchu, TW;

Inventors:

Yung-Cheng Ma, Hsinchu, TW;

I-Yen Chen, Kaohsiung, TW;

Yen-Tun Peng, Taipei, TW;

Chi-Lung Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/00 (2006.01); G06F 15/00 (2006.01); G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is directed to a speed-level calculator and calculating method for dynamic voltage scaling. The speed-level calculator comprises a deadline counter, a shifter, and a fixed-point multiplier. The deadline counter calculates the residual time D from current time to each task deadline for completing an episode. The shifter generates a D' value by shifting the D value to the right for e-m bits, and takes the decimal fraction part of the D′ value for m bits. The speed-level calculator further comprises a saturation control circuit to detect if an overflow occurs on the D′ value. According to a pre-calculated parameter αcorresponding to each task T, the fixed-point multiplier performs the multiplication of D′ and α. After completing saturation and rounding on the multiplication result, a corresponding clock period is generated by taking the integer part. This clock period is used as speed-level to switch the processor voltage and frequency.


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