Measurement of partially depleted silicon-on-insulator cmos circuit leakage current under different steady state switching conditions

Abstract

A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.