The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2012

Filed:

Jun. 30, 2009
Applicants:

Jun-hyeub Sun, Gyeonggi-do, KR;

Shi-young Lee, Gyeonggi-do, KR;

Jong-sik Bang, Gyeonggi-do, KR;

Sang-min Ju, Gyeonggi-do, KR;

Inventors:

Jun-Hyeub Sun, Gyeonggi-do, KR;

Shi-Young Lee, Gyeonggi-do, KR;

Jong-Sik Bang, Gyeonggi-do, KR;

Sang-Min Ju, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor, Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C 1/22 (2006.01); H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for performing a double pattering process of a semiconductor device is provided. The method includes forming a hard mask layer having a stack structure of a first layer, a second layer and a third layer in sequence, forming a first photoresist pattern over the hard mask layer, etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier, forming a second photoresist pattern over the third layer patterns, etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier, removing the second photoresist pattern, and etching the first layer to form first layer patterns by using the second layer patterns as an etch barrier.


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