The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2012

Filed:

Sep. 30, 2009
Applicants:

Steven C. Rudy, San Jose, CA (US);

Eric R. Mckie, Pleasanton, CA (US);

Mark D. Moravec, Gilroy, CA (US);

Inventors:

Steven C. Rudy, San Jose, CA (US);

Eric R. Mckie, Pleasanton, CA (US);

Mark D. Moravec, Gilroy, CA (US);

Assignee:

Western Digital (Fremont), LLC, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/127 (2006.01); H04R 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for modeling devices in a wafer comprises the step of providing the wafer comprising a first plurality of devices having a track width and a first stripe height, a second plurality of devices having the track width and a second stripe height, and a third plurality of devices having the track width and a third stripe height. The method further comprises the steps of measuring resistance values for the first, second and third plurality of devices to obtain a data set correlating a stripe height and a resistance value for each of the first, second and third plurality of devices, and estimating a linear relationship between resistance and inverse stripe height for the first, second and third plurality of devices based on the data set.


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