The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2012
Filed:
Nov. 03, 2008
Leijun HU, Jinan, CN;
Yong Dou, Jinan, CN;
Guangming Liu, Jinan, CN;
Endong Wang, Jinan, CN;
Xiangke Liao, Jinan, CN;
Jun Luo, Jinan, CN;
Hongwei Yin, Jinan, CN;
Qingbo Wu, Jinan, CN;
Yongwen Wang, Jinan, CN;
Shouhao Wang, Jinan, CN;
Jiaming Huang, Jinan, CN;
Jizhi Zhao, Jinan, CN;
Yi Zheng, Jinan, CN;
Leijun Hu, Jinan, CN;
Yong Dou, Jinan, CN;
Guangming Liu, Jinan, CN;
Endong Wang, Jinan, CN;
Xiangke Liao, Jinan, CN;
Jun Luo, Jinan, CN;
Hongwei Yin, Jinan, CN;
Qingbo Wu, Jinan, CN;
Yongwen Wang, Jinan, CN;
Shouhao Wang, Jinan, CN;
Jiaming Huang, Jinan, CN;
Jizhi Zhao, Jinan, CN;
Yi Zheng, Jinan, CN;
Abstract
A close-coupling shared storage architecture of double-wing expandable multiprocessor is provided in the close-coupling shared storage architecture with p processors scale, the close-coupling shared storage architecture of double-wing expandable multiprocessor comprises: j processor modules PMs; wherein, each processor module is formed by coupling and cross-jointing i processors Cs, and each processor is directly connected with a node controller NC through only one link; each processor module PM comprises 2 pairing node controllers NCs, and each node controller NC is connected with the processors through m links and is connected with an interconnect network through n links; the interconnect network comprises two groups, and each group comprises k cross switch route chips NRs, each of which has q ports. By adopting the connection method above, the close-coupling shared storage architecture of double-wing expandable multiprocessor is formed. On the premise that the processor scale is kept expandable, the balance between the processor bandwidth and the network bandwidth is achieved, and the lower average delay of the interconnect network is kept simultaneously.