The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2012
Filed:
Dec. 23, 2010
Kanji Otsuka, Higashiyamato, JP;
Tsuneo Ito, Ome, JP;
Yoichi Sato, Iruma, JP;
Masahiro Yoshida, Hamura, JP;
Shigeru Yamamoto, Hachioji, JP;
Takeshi Koyama, Ome, JP;
Yuko Tanba, Ome, JP;
Yutaka Akiyama, Hachioji, JP;
Kanji Otsuka, Higashiyamato, JP;
Tsuneo Ito, Ome, JP;
Yoichi Sato, Iruma, JP;
Masahiro Yoshida, Hamura, JP;
Shigeru Yamamoto, Hachioji, JP;
Takeshi Koyama, Ome, JP;
Yuko Tanba, Ome, JP;
Yutaka Akiyama, Hachioji, JP;
Other;
Abstract
A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memoriesincluding basic cellsarranged in a cluster, the basic cellincluding a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memorieslocated along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibusincluding a through-via, an arbitrary one of the basic cellsis directly accessed through the multibusfrom the controller chip so that truth value data is written therein, and whereby the arbitrary basic cellis switched to a logic circuit as conjugate.