Gate driving circuit of display panel including shift register sets

Abstract

A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.