The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2012

Filed:

Jul. 07, 2010
Applicants:

Elmar Gaugler, Boeblingen, DE;

Wilhelm Haller, Boeblingen, DE;

Friedhelm Kessler, Boeblingen, DE;

Inventors:

Elmar Gaugler, Boeblingen, DE;

Wilhelm Haller, Boeblingen, DE;

Friedhelm Kessler, Boeblingen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.


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