The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Sep. 07, 2010
Christian Habermann, Stuttgart, DE;
Christian Jacobi, Boeblingen, DE;
Matthias Pflanz, Holzgerlingen, DE;
Hans-werner Tast, Boblingen, DE;
Ralf Winkelmann, Boblingen, DE;
Christian Habermann, Stuttgart, DE;
Christian Jacobi, Boeblingen, DE;
Matthias Pflanz, Holzgerlingen, DE;
Hans-Werner Tast, Boblingen, DE;
Ralf Winkelmann, Boblingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.