The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Jun. 25, 2008
Vi Chi Chan, Hong Kong, HK;
Tetse Jang, San Jose, CA (US);
Kevin Chung, Toronto, CA;
Taneem Ahmed, Toronto, CA;
David Nguyen Van Mau, Syssinet, FR;
Mehrdad Parsa, Santa Cruz, CA (US);
Amit Singh, San Jose, CA (US);
Vi Chi Chan, Hong Kong, HK;
Tetse Jang, San Jose, CA (US);
Kevin Chung, Toronto, CA;
Taneem Ahmed, Toronto, CA;
David Nguyen Van Mau, Syssinet, FR;
Mehrdad Parsa, Santa Cruz, CA (US);
Amit Singh, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first choice network. At least a second choice network can be generated from the first choice network according to a second synthesis technique. A placement for the second choice network can be determined. The placement for the first choice network can be compared with the placement for the second choice network. A placement and corresponding choice network can be selected according to the comparison, and output.