The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Aug. 10, 2009
Daniel E. Mazuk, Marion, IA (US);
Clifford R. Klein, Marion, IA (US);
Daniel J. Goiffon, Cedar Rapids, IA (US);
Neal J. Bohnenkamp, Cedar Rapids, IA (US);
Charles F. Steffen, Cedar Rapids, IA (US);
David A. Miller, Swisher, IA (US);
Robert H. Pulju, Cedar Rapids, IA (US);
Daniel E. Mazuk, Marion, IA (US);
Clifford R. Klein, Marion, IA (US);
Daniel J. Goiffon, Cedar Rapids, IA (US);
Neal J. Bohnenkamp, Cedar Rapids, IA (US);
Charles F. Steffen, Cedar Rapids, IA (US);
David A. Miller, Swisher, IA (US);
Robert H. Pulju, Cedar Rapids, IA (US);
Rockwell Collins, Inc., Cedar Rapids, IA (US);
Abstract
A multi-core processor system including a main processor, an internal EPON bus, and a plurality of secondary core processors. The main processor includes a processing unit; an offload engine operatively connected to the processing unit for routing data to and from the processing unit; a plurality of main processor optical network units (ONU's) operatively connected to the offload engine; and, a dual optical line terminal (OLT) operatively connected to the offload engine. The internal EPON bus is operatively connected to the OLT. The plurality of secondary core processors are located physically separate from the main processor, each secondary core processor having a respective secondary core processor ONU being operatively connected to the main processor via the internal EPON bus. A number of the multi-core processor systems can be used to form an integrated modular avionics (IMA) system when operatively connected to remote data concentration components via an external EPON bus connected to the dual OLTs of the multi-core processor systems.