The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2012

Filed:

Mar. 25, 2010
Applicants:

Chung Kuang Chin, Saratoga, CA (US);

Edward E. Sprague, Woodside, CA (US);

Prasad Paranjape, Fremont, CA (US);

Swaroop Raghunatha, Milpitas, CA (US);

Venkat Talapaneni, Cupertino, CA (US);

Inventors:

Chung Kuang Chin, Saratoga, CA (US);

Edward E. Sprague, Woodside, CA (US);

Prasad Paranjape, Fremont, CA (US);

Swaroop Raghunatha, Milpitas, CA (US);

Venkat Talapaneni, Cupertino, CA (US);

Assignee:

Infinera Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available.


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