The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2012

Filed:

Feb. 20, 2008
Applicants:

Sung-ho Jang, Gyeonggi-do, KR;

Yong-jin Choi, Gyeonggi-do, KR;

Min-sung Kang, Gyeonggi-do, KR;

Kwang-woo Lee, Gyeonggi-do, KR;

Inventors:

Sung-Ho Jang, Gyeonggi-do, KR;

Yong-Jin Choi, Gyeonggi-do, KR;

Min-Sung Kang, Gyeonggi-do, KR;

Kwang-Woo Lee, Gyeonggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.


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