The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Mar. 31, 2010
Manolito M. Catalasan, Mission Viejo, CA (US);
Vafa J. Rakshani, Newport Coast, CA (US);
Edmund H. Spittles, Wiltshire, GB;
Tim Sippel, Portland, OR (US);
Richard Unda, Fullerton, CA (US);
Manolito M. Catalasan, Mission Viejo, CA (US);
Vafa J. Rakshani, Newport Coast, CA (US);
Edmund H. Spittles, Wiltshire, GB;
Tim Sippel, Portland, OR (US);
Richard Unda, Fullerton, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a 'Meta-Memory Cell' (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.