Efficient context switching of virtual processors by managing physical register states in a virtualized environment

Abstract

Various operations are disclosed for improving the operational efficiency of register handling in a virtualized environment. Some infrequently accessed software managed registers are managed lazily when switching contexts between virtual processors. The states of those registers are not saved on exit from a guest or restored on entry to the guest. Rather, guest accesses to those registers are intercepted. For some frequently accessed registers, register states are saved or restored only upon exit from a hypervisor to a different guest that that from which the hypervisor was entered. For enable-flag-gated registers, updates to a physical register value are not made unless the register is enabled. A shadow register cache may be used to speed accesses to some registers. When a shadowed register is modified, the new value is cached as a shadow copy in RAM and subsequent reads of the register are taken from the shadow copy.