The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2012

Filed:

Jan. 13, 2012
Applicants:

Tung-chieh Chen, Taipei, TW;

Bo-wei Chen, New Taipei, TW;

Ta-yu Kuan, Taitung County, TW;

Inventors:

Tung-Chieh Chen, Taipei, TW;

Bo-Wei Chen, New Taipei, TW;

Ta-Yu Kuan, Taitung County, TW;

Assignees:

Springsoft Inc., Hsinchu, TW;

Springsoft USA, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a computer-implemented method to generate a placement for a plurality of device modules within an analog integrated circuit (IC) subject to a set of constraints. By building a constraint hierarchy tree according to the constraints, conflicts of constraints can be identified and resolved. Furthermore, placements can be generated based on the hierarchy tree through a bottom-to-top dimension optimization process and a top-down wire length optimization process. Furthermore, a graphical user interface can be used to display the tree, and the user can edit the tree visually and interactively.


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