Read command triggered synchronization circuitry

Abstract

A system having a processor, a memory controller coupled to said processor, a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller and at least one of said DRAM chips comprising a clock synchronization circuit to receive a reference clock signal and to output a synchronized clock output signal. The system has a plurality of signal buses coupling the processor to the memory controller and the memory controller to said DRAM chips. The signal line conveys signals from said memory controller to said clock synchronization circuit to turn on and off the clock synchronization circuit according to control logic. A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.