The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
May. 17, 2010
Woogeun Rhee, Beijing, CN;
Xueyi Yu, Beijing, CN;
Joon-young Park, Seoul, KR;
Zhihua Wang, Beijing, CN;
Woogeun Rhee, Beijing, CN;
Xueyi Yu, Beijing, CN;
Joon-Young Park, Seoul, KR;
Zhihua Wang, Beijing, CN;
Samsung Electronics Co., Ltd., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals. The second delay locked loop receives the data signal, the selected second clock signal, and the plurality of phase resolution control signals, generates a plurality of third clock signals having variable phase resolution based on the selected second clock signal and at least one of the plurality of phase resolution control signals, and performs a locking operation on the plurality of third clock signals and the data signal.